Thin-Body Silicon FET Devices and Technology

Continued miniaturization of bulk silicon CMOS transistors is being limited by degrading short channel effects. Traditionally, higher channel doping, shallower source/drain junctions, and thinner gate dielectrics have been employed to improve gate control and enhance performance as the gate length is scaled down. However, these techniques are rapidly approaching material and process limits. Alternate transistor architectures such as the planar ultra-thin body (UTB) FET and double-gate MOSFET may be necessary to continue gate length scaling down to the sub-10nm regime.